1. Field of the Invention
The present invention generally relates to a computer with a vector processor having a masking function, in which there are provided mask registers storing mask data indicating, in the array element unit, whether or not an IF/ELSE statement specified in a program should be applied and vector operation processing is controlled on the basis of the mask data stored in the mask registers. More particularly, the present invention is concerned with a computer with a vector processor having a masking function capable of executing vector operation processing according to the mask data with respect to a program having the structure of IF/ELSE statements which are nested with the level of nesting less than the number of mask registers.
A computer with a vector processor having the masking function is designed to efficiently process the operation of an IF/ELSE statement in a program in a pipeline manner. For example, the computer is equipped with mask registers storing mask data indicating, in the array element unit, whether or not the IF/ELSE statement should be applied. The vector operation is executed by means of the masking function using the mask data. That is, an operation on the array elements indicated by the mask data so that the IF/ELSE statement should be applied to these array elements is validated.
Computers with the vector processors having the masking function as described above are required to have a structure enabling the masking function even if IF/ELSE statements are nested.
2. Description of the Prior Art
As described above, a computer with a vector processor having the masking function performs the vector operation utilizing the masking function which allows execution of an operation on the array elements indicated by the mask data so that an IF/ELSE statement may be applied thereto, the mask data stored in the mask register indicating, in the array element unit, whether or not the IF/ELSE statement should be applied.
A program having an IF statement shown in FIG. 1 will now be considered. FIG. 2 shows processing of a vector operation with the masking function carried out when the program shown in FIG. 1 is executed. FIG. 2 shows a vector register VR storing array elements of vector data A indicating a positive value, and another vector register VR storing array elements of vector data B. A mask register MR has storage areas (entry positions corresponding to the storage areas of the vector registers VR). True values "0" of mask data, indicating that the IF statement should be applied to array elements of vector data A, or false values "1" of mask data indicating that the IF statement should not be applied to array elements of vector data A, are written into the entry positions of the mask register MR. Regarding the array elements of vector data A indicated as the true values by the mask data stored in the mask register MR, vector addition operations on these array elements of vector data A and corresponding array elements of vector data B are executed, and the resultant array elements are written, as vector data C, into the vector register VR.
In the example shown in FIG. 2, the addition operation on array elements A(1) and B(1) is executed and resultant vector data C(1) is written into the vector register VR. Similarly, the addition operation on array elements A(3) and B(3) is executed and resultant vector data C(3) is written into the vector register VR.
FIG. 3 shows a program having an ELSE statement. The mask data indicating whether or not the ELSE statement should be applied is the inverted version of the mask data for the IF statement related to the above ELSE statement.
Generally, in order to cope with IF/ELSE statements which are nested, conventional computers with vector processors having the masking function 10 are designed to have more mask registers than the level of nesting. However, a limited number of mask registers can be provided due to the scale of hardware.
In the prior art, if nesting of IF/ELSE statements having a level greater than the number of mask registers takes place, the mask registers cannot be used. In this case, the use of the vector processor is abandoned and the related program must be performed by a scaler operation. This means that the capability of the high-speed pipelines achieved by the vector processor cannot be utilized and the operation cannot be executed at high speeds.